As the demand for higher data rates and bandwidth requirements continues to increase, various technologies facilitating transmission rates of the order of about 10 Gigabits and higher are being developed for high-speed network applications. High-speed digital communication networks over copper and optical fiber are typically used in many network communication and digital storage applications. Ethernet and Fiber Channel, for example, are two widely used communication protocols which continue to evolve in response to an ever increasing need for higher bandwidth in digital communication systems. Accordingly, there is a need to develop various Gigabit networking devices that may facilitate, for example, high-speed serial data applications. The IEEE P802.3ae draft 5 specification describes the physical layer requirements for 10 Gigabit Ethernet applications and is incorporated herein by reference in its entirety.
The Open Systems Interconnection (OSI) model (ISO standard) was developed to establish standardization for linking heterogeneous computer and communication systems. It describes the flow of information from a software application of a first computer system to a software application of a second computer system through a network medium. The OSI model has seven distinct functional layers including Layer 7: an application layer; Layer 6: a presentation layer; Layer 5: a session layer; Layer 4: a transport layer; Layer 3: a network layer; Layer 2: a data link layer; and Layer 1: a physical layer. Importantly, each OSI layer describes certain tasks which are necessary for facilitating the transfer of information through interfacing layers and ultimately through the network. Notwithstanding, the OSI model does not describe any particular implementation of the various layers.
OSI layers 1 to 4 generally handle network control and data transmission and reception. Layers 5 to 7 may be adapted to handle various application issues. Specific functions of each layer may vary depending on factors such as protocol and interface requirements or specifications that are necessary for implementation of a particular layer. For example, the Ethernet protocol may provide collision detection and carrier sensing in the data link layer. Layer 1, the physical layer, is responsible for handling all electrical, optical, opto-electrical and mechanical requirements for interfacing to the communication media. Notably, the physical layer may facilitate the transfer of electrical signals representing an information bit stream. The physical layer may also provide services such as, encoding, decoding, synchronization, clock data recovery, and transmission and reception of bit streams. In high bandwidth applications having transmission speeds of the order of Gigabits, high-speed electrical, optical and/or electro-optical transceivers may be used to implement this layer.
The proliferation of physical layer devices designed to meet the needs of high speed communication applications will, without a doubt, give rise to new challenges. One challenge pertains to the development of circuits that may be adapted to support the high speed communications devices having optimized power consumption. In this regard, various attempts have been made to provide standardized power management procedures for various network devices and/or applications. To ensure proper operation of these high speed communication devices, power control or power management circuits are required for efficiently transitioning the device between various processing states.
The network driver interface specification (NDIS) defines a standardized network application programming interface (API) that provides standardized power management procedures for network interface cards (NICs). In this regard, the NDIS provides a medium access control (MAC) driver that encapsulates or wraps the complexity and details of a network interface card and provides a common application programming interface for accessing various functions of a network interface card. For example, NDIS provides a standardized API that may be used to access Ethernet-based network interface cards.
NDIS also provides a suite or library of functions, which may be adapted as tools that may be used to access the functionality of a network interface card. The suite or library of functions provided by the NDIS may be utilized by various upper level protocol drivers, thereby reducing the complexity of these upper level drivers. For example, a MAC layer driver or even transmission control protocol/internet protocol (TCP/IP) driver may utilize one or more functions of NDIS suite or library of functions.
FIG. 1 is a high-level block diagram of an exemplary NDIS architecture 100. Referring to FIG. 1, there is shown a hardware block 102, a protocol stack 104, a driver block 106, and an application block 108. The hardware block 102 may include the necessary hardware that may be utilized for communicating over a transport medium. Accordingly, the hardware block 102 may include, for example, various integrated circuits and suitable logic that may be adapted to transmit and/or receive signals from a transport medium.
The protocol stack block 104 may be adapted to provide a layered architecture that defines particular functionality and services offered by each layer in the architecture. Specifically, the protocol stack block 104 may be consistent with the layered architecture of the OSI.
The driver block 106 may include a hardware specific driver block 110 and/or a miniport driver block 112. In general, the hardware specific driver block 110 may be adapted to provide platform or hardware specific functionality. In this regard, the use of the hardware specific driver block 110 by non-native applications may be limited and in some instances, some non-native applications may not have the capability to interface with the hardware specific driver block 110. The latter may be particularly true in instances where the hardware specific driver block 110 is proprietary. In general, the miniport driver block 112 may be adapted to provide platform independent functionality such as wrapper functions. In this regard, the miniport driver block 112 may conform to certain standards and may be adapted to provide universal functions, which may be utilized by both native and non-native applications.
The application block 108 may include one or more software applications and/or functions that may be adapted to handle the communication of data received and/or transmitted by the hardware block 102. Applications in the application block 108 may be adapted to utilize the standardized wrapper functions provided by the miniport driver block 112 and/or the proprietary drivers provided by the hardware specific driver block 110. Applications in the application block 108 may utilize various functions provided by either of the hardware specific driver block 110 or the miniport driver block 112 to handle connections, process messages received by the hardware block 102 and messages to be transmitted by the hardware block 102.
For power management purposes, a network controller, such as an Ethernet medium access control (MAC) device, may be required to generate a power management event upon the receipt of certain network events. Those events may include, but are not limited to, network status changes, a management request, receipt of a network wakeup frame and receipt of a magic packet. In general, a wakeup frame may be any specified frame, also called an interested frame, that may be used to wakeup a system.
Particularly, a network wakeup event may be a hardware or software generated request, which may be used to initiate a change in power state of a system or system component or entity. For example, a network wakeup event may be utilized for changing the state of a system and/or device from a lowered powered state to a fully powered state, or vice versa. In general, network wakeup events may be generated external to a network. Exemplary network wakeup frames may include address resolution protocol (ARP) broadcast frames, directed uni-cast frames and NetBIOS broadcast frames.
In some networking applications, depending on the network vendor, some software and/or hardware applications may require the use of a network device capable of recognizing wakeup frames based on pattern matches that may occur anywhere in the first 128 bytes of the frame. Such an implementation may add excessive cost to the hardware required for the network interface controller and/or card (NIC), since additional memory and/or buffers may be required. Furthermore, since additional software programming is required to control the functionality of the network interface card, the programming overhead may further increase the cost associated with the network interface card. Moreover, in Gigabit Ethernet (GbE) wire-speed applications, these associated costs can obviously be prohibitively high. Due to the rapid growth in networking technology, a flexible power management solution is required that will not only meet current power management requirements, but will also be expandable so that it will be applicable to more advanced future networking applications.
Some conventional systems utilize rather large power monitoring circuits to aid in managing the power among the various operating states of the high speed communication devices. However, these large circuits are often complicated and not readily adaptable to the continuously varying power conditions experienced by these devices. The design of some of these power monitoring and management circuitry are often inflexible and may not be readily scaled or adapted to operate in other processing environments or on other platforms. For example, in certain instances, improper switching may result in current flowing back into a main voltage source, thereby increasing an input voltage to an undesired level. This may cause current levels to exceed various specification threshold levels. Depending on the system, this may cause the system to hang or be reset.
Furthermore, these conventional power control circuits may vastly increase the cost of processing because of the space which these power control circuits may occupy on printed circuit boards (PCBs). Since printed circuit board real estate is expensive and scarce, designers find it desirable to maximize the use of printed circuit boards by devoting as much of the real estate as possible to processing.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.